Foundations and Trends® in Electronic Design Automation > Vol 11 > Issue 1-2

Secure Processors Part I: Background, Taxonomy for Secure Enclaves and Intel SGX Architecture

Victor Costan, Massachusetts Institute of Technology, USA, victor@costan.us Ilia Lebedev, Massachusetts Institute of Technology, USA, ilebedev@mit.edu Srinivas Devadas, Massachusetts Institute of Technology, USA, devadas@mit.edu
 
Suggested Citation
Victor Costan, Ilia Lebedev and Srinivas Devadas (2017), "Secure Processors Part I: Background, Taxonomy for Secure Enclaves and Intel SGX Architecture", Foundations and Trends® in Electronic Design Automation: Vol. 11: No. 1-2, pp 1-248. http://dx.doi.org/10.1561/1000000051

Published: 13 Jul 2017
© 2017 V. Costan, I. Lebedev, and S. Devadas
 
Subjects
System level design,  Security and privacy
 

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In this article:
1. Introduction
2. A Primer on Computer System Architecture
3. A Primer on Security for Trusted Processors
4. A Survey of Secure Processors
5. The Software Isolation Container (As Exemplified by Intel’s SGX)
6. Conclusion
Acknowledgments
References

Abstract

This manuscript is the first in a two part survey and analysis of the state of the art in secure processor systems, with a specific focus on remote software attestation and software isolation. This manuscript first examines the relevant concepts in computer architecture and cryptography, and then surveys attack vectors and existing processor systems claiming security for remote computation and/or software isolation. This work examines in detail the modern isolation container (enclave) primitive as a means to minimize trusted software given practical trusted hardware and reasonable performance overhead. Specifically, this work examines in detail the programming model and software design considerations of Intel’s Software Guard Extensions (SGX), as it is an available and documented enclave-capable system. Part II of this work is a deep dive into the implementation and security evaluation of two modern enclave-capable secure processor systems: SGX and MIT’s Sanctum. The complex but insufficient threat model employed by SGX motivates Sanctum, which achieves stronger security guarantees under software attacks with an equivalent programming model. This work advocates a principled, transparent, and well-scrutinized approach to secure system design, and argues that practical guarantees of privacy and integrity for remote computation are achievable at a reasonable design cost and performance overhead.

DOI:10.1561/1000000051
ISBN: 978-1-68083-300-3
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ISBN: 978-1-68083-301-0
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Table of contents:
1. Introduction
2. A Primer on Computer System Architecture
3. A Primer on Security for Trusted Processors
4. A Survey of Secure Processors
5. The Software Isolation Container (As Exemplified by Intel’s SGX)
6. Conclusion
Acknowledgments
References

Secure Processors Part I: Background, Taxonomy for Secure Enclaves and Intel SGX Architecture

This monograph is the first in a two-part survey and analysis of the state of the art in secure processor systems, with a specific focus on remote software attestation and software isolation. It first examines the relevant concepts in computer architecture and cryptography, and then surveys attack vectors and existing processor systems claiming security for remote computation and/or software isolation. It examines, in detail, the modern isolation container (enclave) primitive as a means to minimize trusted software given practical trusted hardware and reasonable performance overhead. Specifically, this work examines the programming model and software design considerations of Intel’s Software Guard Extensions (SGX), as it is an available and documented enclave-capable system.

This work advocates a principled, transparent, and well-scrutinized approach to secure system design, and argues that practical guarantees of privacy and integrity for remote computation are achievable at a reasonable design cost and performance overhead.

 
EDA-051

Companion

Secure Processors Part II: Intel SGX Security Analysis and MIT Sanctum Architecture , Foundations and Trends® in Electronic Design Automation, Volume 11, Issue 3 10.1561/1000000052