Design Automation of Real-Life Asynchronous Devices and Systems
Foundations and Trends® in
Electronic Design Automation
Volume 2 Issue 1
DOI: 10.1561/1000000006
Design Automation of Real-Life Asynchronous Devices and Systems
Alexander Taubin
Boston University, USA, taubin@bu.edu
Jordi Cortadella
Universitat Polit ècnica de Catalunya, Spain, jordi.cortadella@upc.edu
Luciano Lavagno
Politecnico di Torino, Italy, lavagno@polito.it
Alex Kondratyev
Cadence Design Systems, USA, kalex@cadence.com
Ad Peeters
Handshake Solutions, The Netherlands, ad.peeters@handshakesolutions.com
SUGGESTED CITATION:
Alexander
Taubin
Jordi
Cortadella
Luciano
Lavagno
Alex
Kondratyev
Ad
Peeters
(2007)
"Design Automation of Real-Life Asynchronous Devices and Systems",
Foundations and Trends® in
Electronic Design Automation: Vol. 2: No 1, pp 1-133.
http:/dx.doi.org/10.1561/1000000006
Abstract
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at
the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations
and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant
overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives.
However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable
exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to
the synchronous RTL-to-GDSII flow) for asynchronous circuits.
The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows
that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and
it is one of the oldest from a methodological point of view.
The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together
as asynchronous re-implementations of synchronous (RTL- or gate-level) specifications. The main common idea is substituting
the global clocks by local synchronizations. Their most important aspect is to open the possibility to implement large legacy
synchronous designs in an almost “push button” manner, where all asynchronous machinery is hidden, so that synchronous RTL
designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations,
to very high performance, extremely robust dual-rail pipelines.