Foundations and Trends® in Electronic Design Automation > Vol 4 > Issue 1

Manufacturability Aware Routing in Nanometer VLSI

David Z. Pan, ECE Dept., University of Texas, USA, Minsik Cho, Logic and Synthesis Dept., IBM Research, USA, Kun Yuan, ECE Dept., University of Texas, USA,
Suggested Citation
David Z. Pan, Minsik Cho and Kun Yuan (2010), "Manufacturability Aware Routing in Nanometer VLSI", Foundations and Trends® in Electronic Design Automation: Vol. 4: No. 1, pp 1-97.

Published: 04 May 2010
© 2010 D. Z. Pan, M. Cho and K. Yuan
Circuit Level Design

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In this article:
1 Introduction
2 CMP Aware Routing
3 Random-Defect Aware Routing
4 Lithography Aware Routing
5 Redundant-Via Aware Routing
6 Antenna-Effect Aware Routing
7 Other DFM Issues in VLSI Routing
8 Conclusions


This monograph surveys key research challenges and recent results of manufacturability aware routing in nanometer VLSI designs. The manufacturing challenges have their root causes from various integrated circuit (IC) manufacturing processes and steps, e.g., deep sub-wavelength lithography, random defects, via voids, chemical–mechanical polishing, and antenna effects. They may result in both functional and parametric yield losses. The manufacturability aware routing can be performed at different routing stages including global routing, track routing, and detail routing, guided by both manufacturing process models and manufacturing-friendly rules. The manufacturability/yield optimization can be performed through both correct-by-construction (i.e., optimization during routing) and construct-by-correction (i.e., post-routing optimization). This monograph will provide a holistic view of key design for manufacturability issues in nanometer VLSI routing.

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Table of contents:
1: Introduction
2: CMP Aware Routing
3: Random-Defect Aware Routing
4: Lithography Aware Routing
5: Redundant Via Aware Routing
6: Antenna-Effect Aware Routing
7: Other DFM Issues in VLSI Routing
8: Conclusions

Manufacturability Aware Routing in Nanometer VLSI

Nanometer very large scale integrated (VLSI) circuit design faces tremendous challenges due to the manufacturing limitations. These manufacturing and process related challenges include the printability issues due to deep sub-wavelength lithography, the topography variations due to chemical-mechanical polishing (CMP), the random defects due to missing or extra material, and so on. Thus, design "closure" may not automatically guarantee the manufacturing closure due to the manufacturing yield loss. Manufacturability aware layout optimization plays a key role in the overall yield improvement. Manufacturability Aware Routing in Nanometer VLSI examines key aspects of manufacturability issues and how to alleviate them during the routing stage. It shows that various key manufacturability issues can be optimized at different routing stages according to the granularity of routing algorithms and the availability of inputs to models. It surveys both model-based manufacturability optimization and rule-based yield improvement during routing. Existing industry design for manufacturability (DFM) practices mainly rely on either rule-based optimization or post layout enhancement guided by modelling. Manufacturability Aware Routing in Nanometer VLSI demonstrates that there are tremendous opportunities to capture the downstream manufacturing/process effects, and abstract them early into the key physical design stage, through model-based manufacturability aware routing optimization.