Abstract

The rapid development of integrated circuit (IC) technology, driven by the growing demand for Internet of Things (IoT) devices, cloud computing, and cyber-physical systems, has introduced significant challenges in the design and verification of modern System-on-Chip (SoC) systems. Contemporary SoCs, whether used in desktops or servers, are extremely complex with billions of transistors and often use mixed-core technologies. Designing complex SoCs in modern technologies faces issues in scalability, security, verification, and design optimization, especially as the industry transitions to chipset-based architectures. In this work, we explore the potential of deep learning and generative Artificial Intelligence (AI) to address these challenges, focusing on applications in Register Transfer Level (RTL) code generation, design automation, hardware security, and verification.

In this work, we review the state-of-the-art in AI-driven Electronic Design Automation (EDA) tools, examining both open source and commercial platforms that have integrated AI to enhance design efficiency and performance. The work focuses on AI’s role in optimizing power, performance, and area (PPA) metrics, as well as improving hardware security by mitigating threats such as hardware Trojans. In addition, we discuss the implications of adopting AI in SoC workflows and its transformative potential in democratizing hardware design.

Harnessing the Potential of Deep-learning Algorithms and Generative AI for SoC and Chiplet Design and Verification

Recent developments in semiconductor technology have significantly increased integration density, with modern System-on-Chip (SoC) designs for high-performance computing now exceeding 10 billion transistors. However, the traditional CMOS transistor scaling law has reached its physical limits. This has necessitated the adoption of More-than-Moore (MtM) technology, which integrates novel design methodologies and heterogeneous computing architectures. Electronic Design Automation (EDA), design reuse, and IP-based methodologies have been instrumental in bridging the productivity gap, reducing time-to-market, and meeting increasingly stringent performance and security requirements. As electronic systems grow in complexity, new design and verification methodologies are emerging to address these challenges effectively.

In the pre-Internet of Things (IoT) era, the security of SoC designs was often an afterthought. However, the widespread adoption of IoT devices has made security a critical concern at every level of deployment. Current EDA tools, while optimizing for performance, inadvertently introduce vulnerabilities that expose circuits to threats such as side-channel attacks, reverse engineering, and hardware Trojans. This increasing focus on security necessitates the development of security-aware EDA tools capable of addressing threats such as fault injection, information leakage, and timing and power-based attacks.

Deep learning algorithms and Large Language Models (LLMs) have emerged as promising solutions to address the growing challenges in SoC and chiplet design and verification. The application of AI-driven methodologies is revolutionizing Register Transfer Logic (RTL) generation, hardware security, and design automation, leading to enhanced power-performance-area (PPA) metrics and improved verification efficiency. This monograph features three works that explore the transformative role of AI in EDA and SoC design, namely Deep Learning and Generative AI for Monolithic and Chiplet SoC Design and Verification, Large Language Models for EDA, and Evaluating LLMs for Automatic RTL Generation for Combinational Circuits via High-Level Synthesis. These works collectively underscore the transformative potential of AI and LLMs in revolutionizing SoC design and EDA workflows. This monograph provides valuable insights for researchers and industry professionals, inspiring further advancements in AI-assisted hardware design and verification.