Abstract

The ever-growing popularity of large language models (LLMs) has resulted in their increasing adoption for hardware design and verification. Prior research has attempted to assess the capability of LLMs to automate digital hardware design by producing superior-quality Register Transfer Logic (RTL) descriptions, particularly in Verilog. However, these tests have revealed that Verilog code production using LLMs at current state-of-the-art lack sufficient functional correctness to be practically viable, compared to automatic generation of programs in general-purpose programming languages such as C, C++, Python, etc. With this as the key insight, in this work we assess the performance of a two-stage software pipeline for automated Verilog RTL generation for combinational circuits: LLM based automatic generation of annotated C++ code suitable for high-level synthesis (HLS), followed by HLS to generate Verilog RTL. We have benchmarked the performance of our proposed scheme using the open-source VerilogEval dataset, for four different industry-scale LLMs, and the Vitis HLS tool. Our experimental results demonstrate that our two-step technique substantially outperforms previous proposed techniques of direct Verilog RTL generation by LLMs in terms of average functional correctness rates, reaching a score of 0.86 in pass@1 metric.

Harnessing the Potential of Deep-learning Algorithms and Generative AI for SoC and Chiplet Design and Verification

Recent developments in semiconductor technology have significantly increased integration density, with modern System-on-Chip (SoC) designs for high-performance computing now exceeding 10 billion transistors. However, the traditional CMOS transistor scaling law has reached its physical limits. This has necessitated the adoption of More-than-Moore (MtM) technology, which integrates novel design methodologies and heterogeneous computing architectures. Electronic Design Automation (EDA), design reuse, and IP-based methodologies have been instrumental in bridging the productivity gap, reducing time-to-market, and meeting increasingly stringent performance and security requirements. As electronic systems grow in complexity, new design and verification methodologies are emerging to address these challenges effectively.

In the pre-Internet of Things (IoT) era, the security of SoC designs was often an afterthought. However, the widespread adoption of IoT devices has made security a critical concern at every level of deployment. Current EDA tools, while optimizing for performance, inadvertently introduce vulnerabilities that expose circuits to threats such as side-channel attacks, reverse engineering, and hardware Trojans. This increasing focus on security necessitates the development of security-aware EDA tools capable of addressing threats such as fault injection, information leakage, and timing and power-based attacks.

Deep learning algorithms and Large Language Models (LLMs) have emerged as promising solutions to address the growing challenges in SoC and chiplet design and verification. The application of AI-driven methodologies is revolutionizing Register Transfer Logic (RTL) generation, hardware security, and design automation, leading to enhanced power-performance-area (PPA) metrics and improved verification efficiency. This monograph features three works that explore the transformative role of AI in EDA and SoC design, namely Deep Learning and Generative AI for Monolithic and Chiplet SoC Design and Verification, Large Language Models for EDA, and Evaluating LLMs for Automatic RTL Generation for Combinational Circuits via High-Level Synthesis. These works collectively underscore the transformative potential of AI and LLMs in revolutionizing SoC design and EDA workflows. This monograph provides valuable insights for researchers and industry professionals, inspiring further advancements in AI-assisted hardware design and verification.