Discrete gate sizing and threshold assignment are commonly used tools for optimizing digital circuits, and ideal methods for incremental optimization. The gate widths and threshold voltages, along with the gate lengths, can be adjusted to optimize power and delay. This monograph surveys this field, providing the background needed to perform research in the field. Concepts such as standard cell libraries, static timing analysis, and analytical delay and power models are explained, along with examples and data to help understand the tradeoffs involved. Comparative results are also provided to show the current state of the field.
As part of the Physical Design process for digital circuits, the design is mapped to the cells from a given standard cell library. These libraries contain many different variants of each logical function that may vary in transistor widths, lengths, and threshold voltages. Choosing the right cell for each gate in the design is the discrete gate sizing and threshold assignment problem. Discrete gate sizing and threshold assignment are some of the most powerful and commonly used methods for optimizing power/performance/area in digital circuits. Discreteness of the problem makes it computationally difficult and has attracted significant research attention over the past three decades. Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment surveys this field, providing the background needed to understand the problem and perform research in the area. Concepts such as standard cell libraries, static timing analysis, and analytical delay and power models are explained, along with examples and data to help understand the tradeoffs involved. Popular classes of sizing algorithms are explained and comparative results are provided to show the current state of the field. This is an ideal reference text for graduate students and researchers in electronic design automation, and physical designers looking to improve the performance of their designs.